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A low power pulse triggered flipflop (P-FF) design is done by the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. A conditional pulse enhancement technique is devised to speed up the discharge along(More)
A novel conditional clocking flip-flop is proposed. The flip-flop circuit does not consume any power when the data input of the flip-flop does not change its state. Taking the overhead of the auxiliary circuits into account, the flip-flop consumes less power than the conventional flip-flop when the data transition probability is less than 55%. By employing(More)
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