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This paper presents a novel register organization for VLIW DSPs. The simulation results show the performance of a DSP with the proposed register file is comparable with state-of-the-art DSPs. However, the proposed register file can save 89.7% area of a conventional centralized one, while reducing its access time by 68.6%.
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for high-performance real-time DSP applications. But the two major weaknesses in VLIW processors prevent the integration of more functional units (FU) for a higher instruction issuing rate – the dramatically growing complexity in the register file… (More)
As the concurrent functional units in media processors increase continuously to meet the performance needs, the required access (i.e. read or write) ports of the centralized register file (RF) multiply rapidly and cannot be efficiently implemented. We propose a novel ring-structure RF, which is composed of register sub-blocks identical to the RF for a… (More)