Chau-Shen Chen

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We combine technology mapping and placement into a single procedure,, for the design of RAM-based FPGA.s. Iteratively, maps several subnetworks of the boolean network into a number of CLBS on the layout plane simultaneously. For every output node of the un-mapped portion of the boolean network, many ways of mapping are possible. The choice(More)
In an era of sub-micron technology, routing is becoming a dominant factor in area, timing, and power consumption. In this paper, we will study the problem of selecting and chaining of scan ipops with the objective of achieving minimum routing area overhead. Most of previous work on partial scan has put emphasis on selecting as few scan ipops as possible to(More)
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