Learn More
c V dV dJ ρ = = (1) ABSTRACT A physically based model has been formulated to represent temperature-dependent specific contact resistance. The new model can generate silicided contact resistance values at high temperatures and is capable of predicting high current behavior of silicided deep submicron devices. Implications for failure analysis of advanced(More)
Contrary to general understanding, ESD performance of NMOS devices can degrade for shorter channel length transistors in advanced silicided CMOS technologies. In this work, using test structures in a 0.13 µm CMOS process, detailed characterization has been carried out for the first time to comprehend and model the physical mechanism causing this(More)
ESD is a major concern for IC chip quality both from building-in-reliability requirement and from long-term field operation requirement. The damage phenomena, either from human handling or machine contact, could appear as thermal damage and oxide rupture. In this paper, the IC damage phenomena due to ESD, the effects on the IC functionality, the proper(More)
Second breakdown phenomenon in advanced NMOS ESD protection devices has remained an enigma due to the complex electrical and thermal effects that are responsible for its triggering. For the first time, we present a critical study of the high current phenomenon in ultra short-time scale to understand the physics of instability in protection devices around(More)