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c V dV dJ ρ = = (1) ABSTRACT A physically based model has been formulated to represent temperature-dependent specific contact resistance. The new model can generate silicided contact resistance values at high temperatures and is capable of predicting high current behavior of silicided deep submicron devices. Implications for failure analysis of advanced(More)
Contrary to general understanding, ESD performance of NMOS devices can degrade for shorter channel length transistors in advanced silicided CMOS technologies. In this work, using test structures in a 0.13 µm CMOS process, detailed characterization has been carried out for the first time to comprehend and model the physical mechanism causing this(More)
With the continued scaling of technologies the ESD qualification has become a major challenge. This is mainly due to the demand for higher speed circuits, mostly implemented in large high pin count packages, increased SoC applications, along with the newer features of the transistors such as FinFETs. This review paper will present the current perception(More)