Charvaka Duvvury

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Contrary to general understanding, ESD performance of NMOS devices can degrade for shorter channel length transistors in advanced silicided CMOS technologies. In this work, using test structures in a 0.13 μm CMOS process, detailed characterization has been carried out for the first time to comprehend and model the physical mechanism causing this(More)
ESD failure threshold of NMOS transistors is known to degrade with the use of silicided diffusions owing to insufficient ballast resistance, making them susceptible to current localization, which leads to early ESD failure. It is commonly believed that the gate-tocontact spacing of silicided devices has no impact on the ESD strength. However, experimental(More)
A physically based model has been formulated to represent temperature-dependent specific contact resistance. The new model can generate silicided contact resistance values at high temperatures and is capable of predicting high current behavior of silicided deep submicron devices. Implications for failure analysis of advanced silicided devices are also(More)
This paper presents a detailed study of the non-uniform bipolar conduction phenomenon in single finger NMOS transistors and analyses its implications for deep submicron ESD design. It is shown that the uniformity of lateral bipolar triggering is severely degraded with device width (W) in advanced technologies with silicided diffusions and low resistance(More)
A new failure mechanism of PMOSFET devices under ESD conditions is reported and analyzed by investigating various I/O structures. Localized turn-on of the parasitic pnp transistor can be caused by localized charge injection into the body of the PMOSFET. Critical layout parameters affecting this problem are discussed based on 2-D device simulations. A(More)
The specific contact resistance(ρC) at the metal/semiconductor interface is known to be a monotonically decreasing function of temperature. Therefore the temperature dependence of ρC has significant implications for the reliable electrothermal behavior of deep submicron devices under high current and high temperature conditions. In this work, the effect of(More)