Charles J. Poirier

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We describe a program, Excellerator, which automatically generates full custom symbolic CMOS cell layouts. The input is a transistor level netlist with optional constraints on layout shape and IIO port positions. The output is a high quality virtual-grid-based layout suitable for use in a two-dimensional tiling methodology. IIO port locations can be(More)
A VLSI design system called VIVID is the heart of a newly developed, vertically integrated design environment. This environment provides support for all phases of design from high-level system specification through on-site fabrication to construction of prototype systems. Key features already Implemented include: the use of a circuit description language at(More)
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