—We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also… (More)
In this paper we show that an embedded FPGA core is an ideal host to implement infrastructure IP for yield improvement in a bus-based SoC. We present methods for testing, diagnosing, and repairing embedded FPGAs, for which complete testability is achieved without any area overhead or performance degradation. We show how an FPGA core can provide embedded… (More)
This paper proposes a standard set of fault models and establishes acceptable component variations for a new set of benchmark circuits used to evaluate analog and mixed-signal testing techniques.
A Built-In Self-Test (BIST) approach is presented for the configurable logic blocks (CLBs) in Xilinx Virtex-5 Field Programmable Gate Arrays (FPGAs). A total of 17 configurations were developed to completely test the full functionality of the CLBs, including distributed RAM modes of operation. These configurations cumulatively detect 100% of stuck-at faults… (More)
We discuss the development of Built-In Self-Test (BIST) configurations that test all of the programmable logic and interconnect resources in the core of Xilinx 4000E, 4000XL/XLA and Spartan series Field Programmable Gate Arrays (FPGAs). While there has been prior work in BIST for these FPGAs, the fast-carry logic has not been addressed and only a small… (More)
—A system for automatic generation of Built-In Self-Test (BIST) for embedded memory cores in a system-on-chip (SoC) is presented. The BIST approach tests RAMs of any address and data bus widths and can test both single-port and dual-port RAMs operating in synchronous or asynchronous mode. A Field Programmable Gate Array (FPGA) independent BIST model is… (More)