Charles E. Stroud

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We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also(More)
We present the first delay-fault testing approach for Field Programmable Gate Arrays (FPGAs), applicable for on-line testing as well as for off-line manufacturing and system-level testing. Our approach is based on Built-In Self-Test (BIST), it is comprehensive, and does not require expensive external test equipment (ATE). We have successfully implemented(More)
The first built-in self-test (BIST) approach for the programmable input/output (I/O) buffers in field programmable gate arrays (FPGAs) and configurable system-on-chip (SoC) implementations is presented. The I/O buffers are tested for their various modes of operation along with their associated programmable routing sources. A general BIST architecture,(More)
We present the first on-line Built-In Self-Test (BIST) and BIST-based diagnosis of programmable logic resources in Field Programmable Gate Arrays (FPGAs). These techniques were implemented and used in a roving Self-Testing AReas (STARs) approach to testing and reconfiguration of FPGAs for fault-tolerant applications. The BIST approach provides complete(More)