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A simple high-performance nonlinear digital PLL is fabricated in 90 nm CMOS with operating range of 0.5 to 3.25 GHz and 1.24 ps jitter. New insights into the PLL behavior are discussed. The classical “20Log” in-band phase noise tracking does not hold for the type of nonlinear digital loops.
This paper provides a review of the structures and algorithms used in receive end adaptive equalization. These structures are necessary in order to allow high speed signaling over several gigabits per second across a serial backplane channel. As the data rates continue to increase over these channels the causes and the techniques used mitigate interference… (More)