Charles A. Zukowski

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Moving routing tables from RAM to custom or semicustom VLSI can lower cost and boost performance. The routing table problem is presented by discussing the available architectures and how they are related. It is shown that simple table lookup is just a special case of the standard trie structure and that the use of partitioning combined with the trie(More)
We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4x5 array of configurable logic blocks along with programmable interconnect. It can simulate a network of pathways involving up to 20 genes and their associated proteins. The circuit design(More)
In this paper, we investigate the use of monotonic static CMOS logic within a high performance carry lookahead adder (CLA) in the context of a 65nm technology with significant leakage. The goal is a good compromise between speed, power, and noise immunity. We compare the monotonic static CMOS 64b CLA with domino and static CMOS adders with respect to speed(More)
This paper explores the characteristics of Monotonic-Static CMOS and its potential applications in gate leakage reduction in a hypothetical 22nm Bulk-Si technology with significant gate leakage currents. Using test circuits consisting of NAND and NOR logic gates, we performed a comparison among static, monotonic static and domino logic in terms of various(More)
This paper reviews the use of skewed monotonic static CMOS logic gates in scaled technologies where gate leakage currents become significant. High-level tradeoffs and synthesis approaches are discussed, and some experiments are constructed to evaluate the gate-level performance tradeoffs in a hypothetical standard 65nm CMOS technology. At the gate level,(More)