Chao Kun Hu

Learn More
Integration of high porosity low-k dielectrics faces major challenges as the porosity weakens the dielectric, resulting in severe plasma induced damage (PID) and difficulties in profile control. Post porosity plasma protection (P4) integration strategy addresses those challenges by strengthening the dielectric via porosity refill during the integration(More)
Submicron tungsten gate MOSFET with 10 nm gate oxide has been demonstrated for the first time. The results ranging from W stability against SiO<sub>2</sub> to excellent thin oxide MOS properties and high FET transconductance, demonstrate the feasibility and advantages of the tungsten gate for submicron technologies. In applications such as high density(More)
  • 1