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In recent years, the increasing popularity of mobile devices, such as smart- phones and tablets, is driving the demand for integrating multiple radios on a single SoC to reduce cost, form factor and… (More)
This paper presents a 4-way 1.6-GS/s time-interleaved (TI) SAR ADC with fast reference charge neutralization (CN) and background timing-skew calibration. The SAR sub-ADC uses a flip-flop-less digital… (More)
A 3 V, single chip optical receiver analog front-end capable of operating at 2.5 Gbit/s is fabricated in a 0.35 /spl mu/m CMOS technology. The IC contains a transimpedance amplifier (TIA) with 54.5… (More)
This paper presents a SAR ADC using passive noise shaping and noise quantizer techniques. A ping-pong residue switching enables noise shaping at high sampling rate. The prototype in 14 nm achieves… (More)
This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-/spl mu/m digital CMOS process, this integrated… (More)
SAR ADCs are popular in mobile WiFi applications due to their low power and small area. SNR of 60–70dB is necessary to meet the noise budget for the downlink chain in the 802.11 ac/ax standards.… (More)