Chao-Chieh Wu

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In this paper, we developed a high-level simulation model for DRAM controllers to capture such features as burst alignment, scheduling policies, etc. The model is based on SystemC/TLM for ESL platform integration. Compared to a commercial RTL implementation, the model has a worst-case error of 4.5%. Due to its fast simulation speed, we then apply the model(More)
We present a novel design of scalable many-core processor with its comprehensive development framework, including the Electronic System Level, Register Transfer Level, and full-system prototyping platforms. Architecture exploration, performance evaluation and system verification/validation can be done across different abstraction levels. With our(More)
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