Chanhee Oh

Learn More
We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence in average leakage estimation, we introduce the concept of " dominant leakage states " and use state probabilities. Our method achieves speed-ups of 3 to 4 orders of magnitude over(More)
Gate sizing is a practical and a feasible crosstalk noise repair technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. This can create(More)
High performance circuits are facing increasingly severe signal integrity problems due to crosstalk noise and crosstalk noise awareness has become an integral part of static timing analysis (STA). Existing crosstalk noise aware STA methods compute noise induced delay uncertainty on a net by net basis and in a pessimistic way, without considering the overlap(More)
High-performance digital circuits are facing increasingly severe signal integrity problems due to crosstalk noise and therefore the state-of-the-art static timing analysis (STA) methods consider crosstalk-induced delay variation. Current noise-aware STA methods compute noise-induced delay uncertainty for each net independently and annotate appropriate delay(More)
In this paper, we present a new approach to model the impact of cross-coupling noise on interconnect delay. We introduce a new linear driver model that accurately models the noise pulse induced on a switching signal net due to cross coupling capacitance. The proposed model effectively captures the non-linear behavior of the victim driver gate during the(More)
Coupled noise analysis has become a critical issue for deep-submicron, high performance design. In this paper, we present, ClariNet, an industrial noise analysis tool, which was developed to efficiently analyze large, high performance processor designs. We present the overall approach and tool flow of ClariNet and discuss three critical large-processor(More)
—We present a new approach for the estimation and optimization of standby power dissipation in large MOS digital circuits. We first introduce a new approach for accurate and efficient calculation of the average standby or leakage current in large digital circuits by introducing the concepts of " dominant leakage states " and the use of state probabilities.(More)
Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particular node on the subsequent path delay, an earlier signal with a signal slope greater than the slope of the later signal may result in a greater delay. Therefore, the traditional(More)
Power management is an increasing concern for processor design. In this paper, we presented an overview of traditional power simulation tools and discussed two emerging power management design technologies: power distribution integrity analysis and standby current measurement and optimization. We present methods for accurate peak current simulation, which(More)