Chang Yun Park

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We propose a technique for analyzing cache-related preemption delays of tasks that cause unpredictable variation in task execution time in the context of fixed-priority preemptive scheduling. The proposed technique consists of two steps. The first step performs a per-task analysis to estimate cache-related preemption cost for each execution point in a given(More)
Analytic methods are employed at the source-language level, using formal timing schema that include control costs, handle interferences such as interrupts, and produce guaranteed best- and worst-case bounds. The timing tool computes the deterministic execution times for programs that are written in a subset of C and run on a bare machine. Two versions of(More)
This paper describes a method to predict guaranteed and tight deterministic execution time bounds of a sequential program. The basic prediction technique is a static analysis based on simple timing schema for source-level language constructs, which gives accurate predictions in many cases. Using powerful user-provided information, dynamic path analysis(More)
Cache memory is used in almost all computer systems today to bridge the ever increasing speed gap between the processor and main memory. However, its use in multitasking computer systems introduces additional preemption delay due to reloading of memory blocks that were replaced during preemption. This cache-related preemption delay poses a serious problem(More)
We propose an enhanced technique for analyzing and thus, bounding cache-related preemption delay in fixedpriority preemptive scheduling focusing on instruction caching. The proposed technique improves upon previous techniques in two important ways. First, the technique takes into account the relationship between a preempted task and the set of tasks that(More)
An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real-time systems. In RISC processors , the execution time of a program construct (e.g., a statement) is aaected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in(More)
This paper presents a case study of worst case timing analysis for a RISC processor. The target machine consists of the R3000 CPU and R3010 FPA (Floating Point Accelerator). This target machine is typical of a RISC system with pipelined execution units and cache memories. Our methodology is an extension of the existing timing schema. The extended timing(More)