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Though the implementation of the Tate pairing is commonly believed to be computationally more intensive than other cryptographic operations, such as ECC point multiplication, there has been a substantial progress in speeding up the Tate pairing computations. Because of their inherent parallelism, the existing Tate pairing algorithms are very suitable for(More)
We designed hardware accelerators based on Xilinx FPGAs, XCV2000E, to speed up the scalar multiplications on elliptic curves recommended by NIST, over GF (2) and GF (2), in polynomial basis representation. Linear-Feedback-Shift-Registers (LFSRs) are exploited in the most significant digitserial (MSD) multipliers in order to improve design efficiency. We(More)
Tate pairing based cryptosystems have recently emerged as an alternative to traditional public key cryptosystems, because of their ability to be used in multi-party identity-based key management schemes. Due to the inherent parallelism of the existing pairing algorithms, high performance can be achieved via hardware realizations. Three schemes for Tate(More)
[1] Recent theoretical and empirical studies show that the generalization ability of artificial neural networks can be improved by combining several artificial neural networks in redundant ensembles. In this paper, a review is given of popular ensemble methods. Six approaches for creating artificial neural network ensembles are applied in pooled flood(More)
Reconfigurable Computers are general-purpose high-end computers based on a hybrid architecture and close system-level integration of traditional microprocessors and Field Programmable Gate Arrays (FPGAs). In this paper, we present an application of reconfigurable computers to developing a lowlatency implementation of Elliptic Curve Cryptosystems, an(More)
During the last few years, a considerable effort has been devoted to the development of reconfigurable computers, machines that are based on the close interoperation of traditional microprocessors and Field Programmable Gate Arrays. Several prototype machines of this type have been designed, and demonstrated significant speed-ups compared to conventional(More)
Portable libraries of highly-optimized hardware cores can significantly reduce the development time of reconfigurable computing applications. This paper presents the tradeoffs and challenges in the design of such libraries. A set of library development guidelines is provided, which has been validated with the RCLib case study. RCLib is a set of portable(More)
The efficient design of digit-serial multipliers for special binary composite fields, F2nm where gcd(n, m) 1⁄4 1, is presented. These composite fields can be constructed via an irreducible pentanomial of degree nm but not an irreducible trinomial of degree nm. The conventional construction method for such digit-serial multipliers is to exploit the(More)
As Reconfigurable Computing (RC) systems become more common place among application scientists and developers, a mechanism for porting existing work to other platforms is increasingly desirable. The constantly changing technologies and architectures in today’s RC platforms present a challenge to any developer wishing to move from an early development system(More)
This paper describes techniques for the piecewise linear approximation of trimmed NURBS surfaces. The problem, called surface triangulation, arises from many applications in CAD and graphics. The new method generates triangular meshes that are adaptive to the local surface curvature. We use e cient data structures for the handling of trimming curves. We(More)