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- Chang Shu, Soonhak Kwon, Kris Gaj
- FPT
- 2006

Though the implementation of the Tate pairing is commonly believed to be computationally more intensive than other cryptographic operations, such as ECC point multiplication, there has been a substantial progress in speeding up the Tate pairing computations. Because of their inherent parallelism, the existing Tate pairing algorithms are very suitable for… (More)

We designed hardware accelerators based on Xil-inx FPGAs, XCV2000E, to speed up the scalar multiplications on elliptic curves recommended by NIST, over GF (2 163) and GF (2 233), in polynomial basis representation. Linear-Feedback-Shift-Registers (LFSRs) are exploited in the most significant digit-serial (MSD) multipliers in order to improve design… (More)

The efficient design of digit-serial multipliers for special binary composite fields, F 2 nm where gcd(n, m) ¼ 1, is presented. These composite fields can be constructed via an irreducible pentanomial of degree nm but not an irreducible trinomial of degree nm. The conventional construction method for such digit-serial multipliers is to exploit the… (More)

Tate pairing based cryptosystems have recently emerged as an alternative to traditional public key cryptosystems, because of their ability to be used in multi-party identity-based key management schemes. Due to the inherent parallelism of the existing pairing algorithms, high performance can be achieved via hardware realizations. Three schemes for Tate… (More)

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