Chang-Seok Choi

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This paper presents a high-speed lowcomplexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in(More)
In this paper, we propose a soft-decision-based FEC scheme which is the concatenation of a non-binary LDPC (NBLDPC) code and hard-decision FEC code having a compatibility with existing OTU-4 frame structure. The proposed concatenated NB-LDPC + RS frame structure is also provided and the entire frame size is 18,368 bytes. The proposed NB-LDPC(2304,2048) code(More)
This paper presents a high-speed low-complexity three-parallel Reed-Solomon (RS) decoder for 6-Gbps mmWave WPAN systems. Three-parallel processing is used to achieve 6-Gbps data throughput and low hardware complexity. Three-way parallelizing for syndrome computation and error correction allow the inputs to be received at very high data rates and the outputs(More)
An energy-efficient power-aware design is highly desirable for digital signal processing (DSP) functions that encounter a wide diversity of operating scenarios in battery-powered wireless sensor network systems. Addressing this issue, this paper presents a power-aware variable-precision multiply-accumulate (VP-MAC) unit that makes use of dynamic-range(More)
This paper presents a self-reconfigurable adaptive FIR Filter system design using dynamic partial reconfiguration, which has flexibility, power efficiency, configuration time advantage allowing dynamically inserting or removing adaptive FIR filter modules. This self-reconfigurable adaptive FIR filter is responsible for providing the best solution for(More)
This paper presents a novel high-speed low-complexity Folded Degree-Computationless Modified Euclidean (fDCME) algorithm and its architecture for Reed-Solomon (RS) decoders. The proposed scheme uses the fully folded systolic architecture in which two array of processing element computes both the error locator and the error value polynomials. The pipelined(More)