Chang-Hung Yu

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We evaluate and benchmark the performance of logic circuits and stability/performance of 6T SRAM cells using monolayer and bilayer TMD devices based on ITRS 2028 (5.9nm) technology node. For the performance benchmarking of logic circuits, the tradeoff between electrostatic integrity (monolayer favored) and carrier mobility (bilayer favored), and the issues(More)
This work investigates the quantum-capacitance induced drain-current loss for multi-gate In<sub>0.53</sub>Ga<sub>0.47</sub>As n-MOSFETs with tri-gate structure (fin aspect-ratio AR=1) and double-gate FinFET-like structure (AR&gt;&gt;1) through ITRS 2018-2024 technology nodes using quantum-mechanical simulation corroborated by model calculation. The quantum(More)
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