Chandramouli Gopalakrishnan

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We propose a leakage power minimization approach based on Multi-threshold CMOS (MTCMOS) technology. A clique partitioning-based resource allocation and binding algorithm is presented, which maximizes the idle periods of modules in the data-path. Modules with significant idle times are selectively bound to MTCMOS instances. We developed a parameterizable(More)
A study of one hundred consecutive female burns (aged 15-40) admissions into the Department of Plastic Surgery, Madurai Medical College and Government Rajaji Hospital, Madurai revealed 70% to be suicidal, 25% accidental, 3% homicidal ad 2% non-classifiable in nature. The important causes were grouped under psychiatric disorders (23%) physical illness (15%),(More)
We present a fast RTL leakage power simulator for datapaths described hierarchically in VHDL. Only the leafcells such as full adder, NAND gate etc., are characterized for leakage power. At the bit-slice level, exhaustive characterization can be performed in reasonable time. We observed that in the transient state, the leakage power is dependent on the(More)
In this work, we propose two search-based approaches based on the tabu search to explore the solution space for low leakage power data-paths. The first approach explores different schedules. The second approach simultaneously searches for schedules and mappings that dissipate low leakage power. Our approaches identify data-paths which dissipate up to 40%(More)
We present a scheduling, allocation and binding methodology that employs MTCMOS as the standby leakage reduction mechanism. We use the simulated annealing meta-heuristic for optimizing leakage power The cost functions for our approach are obtained after extensive characterization trials taking into account, the run-time characteristics of the MTCMOS(More)
Parsing of large text files has always been a challenge in commercial EDA tools. These files, typically multiple gigabytes in size, are the channels of communication of intermediate data between point-tools working on different parts of the chip design flow. With the advent of multi-core processors, the core algorithms of the EDA tools have been improving(More)
Traditional EDA flows are made up of different point tools stitched together to progress from higher levels of design abstraction to physical level chip details. Data, intent, and constraints are passed on through this flow via intermediate text files. Some of these files such as the Standard Delay Format (SDF) files, are significantly large in size, and(More)