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—In this paper, we propose an architecture that performs the forward and inverse discrete wavelet transform (DWT) using a lifting-based scheme for the set of seven filters proposed in JPEG2000. The architecture consists of two row processors, two column processors, and two memory modules. Each processor contains two adders, one multiplier, and one shifter.(More)
The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a minimum. These implementations are time consuming to design and difficult to verify. A programmable hardware platform capable of supporting software implementations of the physical(More)
In the past decade, the proliferation of mobile devices has increased at a spectacular rate. There are now more than 3.3 billion active cell phones in the world-a device that we now all depend on in our daily lives. The current generation of devices employs a combination of general-purpose processors, digital signal processors, and hardwired accelerators to(More)
This paper presents a wide range of algorithms and architectures for computing the 1-D and 2-D Discrete Wavelet Transform (DWT), and the 1-D and 2-D Continuous Wavelet Transform (CWT). The algorithms and architectures presented here are independent of the size and nature of the wavelet function. New on-line algorithms are proposed for the DWT and the CWT(More)
Recently, aggressive voltage scaling has been shown to be an important technique in achieving highly energy efficient circuits. Specifically, scaling V dd to near or sub-threshold regions has been proposed for energy-constrained sensor systems to enable long lifetime and small system volume [1][2][4]. However, voltage scaling has several limitations,(More)
—As CMOS technology scales down, digital supply voltage and digital power consumption goes down. However, the supply voltage and power consumption of the RF front-end and analog sections do not scale in a similar fashion. In fact, in many state-of-the-art communication transceivers, RF and analog sections can consume more energy compared to the digital(More)
This paper presents accurate area and power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family. These models are designed to facilitate efficient design space exploration in an automated algorithm-architecture codesign framework. Detailed models for accurately estimating the number of slices, block RAMs and 18times18-bit(More)
Hierarchical block matching is an eecient motion estimation technique which provides an adaptation of the block size and the search area to the properties of the image. In this work, we propose two novel special-purpose architectures to implement hierarchical block matching for real-time applications. The rst architecture is memory-eecient, but requires a(More)