Cesar Albenes Zeferino

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The building block of a Network-on-Chip (NoCs) is its router. It is responsible to switch the channels which forward the messages exchanged by the cores attached to the NoC, and the costs and performance of the NoC strongly depends on the router architecture. In this paper, we present RASoC, a router architecture intended to be used in the building of low(More)
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-point bi-directional links between the routers implementing the micro-network. SPIN gives the system designer the simple view of a single shared address space and provides a(More)
Networks-on-Chip (NoCs) emerge as the solution for the problem of interconnecting cores (or IPs) in Systems-on-Chip (SoCs) which require reusable and scalable communication architectures. The building block of a NoC is its router (or switch), whose architecture has great impact on the costs and on the performance of the network. This work presents a(More)
Abstract: The analysis of the communication architecture and its associated synthesis process has grown in importance in the era of System-On-Chip devices, since one is moving towards more complex systems, made by several processing elements (cores), with heterogeneous behavior. In many cases, the choice for a communication architecture can be the most(More)
Present days cores composing a System-on-Chip might be interconnected by means of both dedicated channels or shared buses. Nevertheless, future systems will have strong requirements on reusability and communication performance, which will constrain the use of such interconnect systems. An emerging approach, the Networks-on-Chip (NOCs), will potentially(More)
Networks-on-Chip (NoCs - Networks-on-Chip) have emerged as the best alternative to provide high performance in communication for futures Systems-on- Chip (SoCs) with dozens of cores integrated on a single silicon die. However, the components of a NoC are susceptible to faults resulting from heating, power surge, external radiation and others. Faults in a(More)
Networks-on-Chip (NoCs) are vulnerable to security attacks, which can degrade the network performance, reduce its availability or even block the entire network. In this context, this work aimed at increasing the availability of a NoC by means of the implementation of hardware-based mechanisms that filter malicious packets injected into the network by an(More)