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This letter presents a hybrid approach to efficiently locating data packet errors in an adaptive network-on-chips (NoC). We propose to combine offline and online concepts based on a distributed and factorized online error detection module that will enable us to perform an efficient analysis of partial and localized area networks. This combination allows for(More)
The current evolution of system architectures leads towards implementation of large number of processor cores into the same circuit. This evolution actually supports the performance increase and provides the capability to support the execution of very complex applications. Nevertheless, if these new architectures propose high computational performances, an(More)
Error detection and correction based on double-sampling is used as common technique to handle timing errors while scaling Vdd for energy efficiency. An additional sampling element is inserted in the critical paths of the design, to double sample the outputs of those logic paths at different time instances that may fail while scaling the supply voltage or(More)
In this paper we present a new efficient online routing error detection approach dedicated to fault tolerant routing algorithms for the 2-D mesh reconfigurable Network-on-Chip interconnections. The main contribution is to distinguish a routing error due to switching failure from an adaptative routing decision (bypassing a faulty area or reconfigurable(More)
Voltage scaling has been used as a prominent technique to improve energy efficiency in digital systems, scaling down supply voltage effects in quadratic reduction in energy consumption of the system. Reducing supply voltage induces timing errors in the system that are corrected through additional error detection and correction circuits. In this paper we are(More)