Catherine Bayol

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Working at system level is attracting increasing interest, as it supports the exploration of several alternatives, before the hardware/software partitioning takes place. New issues must be taken into account, such as validation and verification at all steps. Within the framework of a system-level design methodology that supports verification, communication(More)
The VOVHDL language was defined as a verification orietied VHDL-based language in order to obtain a VHDL simulable specification at system level and to be able to verify this specification in a Process Algebra approach. This paper presents a formal semantic model for VOVHDL in terms of parallel composition of Labelled Transition Systems , and its(More)
1. Introduction The boundaries of hardware description are rapidly migrating towards higher and higher levels of abstraction. Until not long ago, designers mainly worked at register-transfer level, whereas new activities at system-level are now emerging. Systems are conceived before partitioning between hardware and software realization takes place, so that(More)
* Working at system level is attracting increasing interest, as it supports the exploration of several alternatives, before the hardware/software partitioning takes place. New issues must be taken into account, such as validation and verification at all steps. This paper presents a system-level design methodology that supports description, validation, and(More)
The VOVHDL language was defined as a verification oriented VHDL–based language in order to obtain a VHDL simulable specification at system level and to be able to verify this specification in a Process Algebra approach. This paper presents a formal semantic model for VOVHDL in terms of parallel composition of Labelled Transition Systems , and its(More)
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