Catherine Bayol

Learn More
The VOVHDL language was defined as a verification orietied VHDL-based language in order to obtain a VHDL simulable specification at system level and to be able to verify this specification in a Process Algebra approach. This paper presents a formal semantic model for VOVHDL in terms of parallel composition of Labelled Transition Systems , and its(More)
* Working at system level is attracting increasing interest, as it supports the exploration of several alternatives, before the hardware/software partitioning takes place. New issues must be taken into account, such as validation and verification at all steps. This paper presents a system-level design methodology that supports description, validation, and(More)
  • 1