Cary K. Chin

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Algorithmic test generation for high fault coverage is an expensive and time-consuming process. As an alternative, circuits can be tested by applying pseudorandom patterns generated by a linear feedback shift register (LFSR). Although no fault simulation is needed, analysis of pseudorandom testing requires the circuit detectability profile. Measures of test(More)
We give a family of examples on which a large class C of "minimum spanning tree-based" rectilinear Steiner tree heuristics has performance ratio arbitrarily close to 3/2 times optimal. The class C contains many published heuristics whose worst-case performance ratio , were previously unknown. Of particular interest is that C contains two heuristics whose(More)
[Pram90] A. Pramanick, S. Reddy, " On the design of path delay fault testable combinational circuits " , Proc. at time t. After the application of the next clock the contents of the even flip-flops of the LFSR are shifted into the odd ones (see Figure 10b) producing the second vector. The content of the first output is derived by XORing the outputs of some(More)
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