Carol Pyron

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Custom VLSI design at the switch level is commonly applied when a chip is required to meet stringent operating requirements in terms of speed, power, or area. ATPG requires gate level models, which are verified for correctness against switch level models. Typically, test models are created manually from the switch level models---a tedious, error-prone(More)
Structural testing with both scan test and Built-in Self-Test (BIST) has proven effective for detecting both gross static and at-speed defects. As tools and techniques improve, structural testing is approaching the high level of test quality necessary to eliminate test escapes. However, scan and BIST do not accomplish all that is needed. Parametric and(More)