Carlos Tokunaga

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Traditional adaptive methods that compensate for PVT variations need safety margins and cannot respond to rapid environmental changes. In this paper, we present a design (RazorII) which implements a flip-flop with in situ detection and architectural correction of variation-induced delay errors. Error detection is based on flagging spurious transitions in(More)
A 45 nm microprocessor core integrates resilient error-detection and recovery circuits to mitigate the clock frequency guardbands for dynamic parameter variations to improve throughput and energy efficiency. The core supports two distinct error-detection designs, allowing a direct comparison of the relative trade-offs. The first design embeds(More)
The maximum operating frequency (Fmax) of a processor is traditionally set at a constant value based on the maximum operating temperature (Tmax) and supply voltage (Vcc) droops. In addition, the expected slowdown of the operating speed during processor lifetime due to transistor aging is used as a guardband for setting the Fmax. The maximum operating(More)
We present a metastability-based True Random Number Generator that achieves high entropy and passes NIST randomness tests. The generator grades the probability of randomness regardless of the output bit value by measuring the metastable resolution time. The system determines the original random noise level at the time of metastability and tunes itself to(More)
Microprocessors experience a wide range of dynamic variations, including voltage droops, temperature changes, and device aging, which vary across applications and systems. The necessity of ensuring correct operation even under infrequent worst-case conditions results in clock frequency (FCLK) or supply voltage (VCC) guardbands that degrade performance and(More)
Hardware implementations of the popular AES encryption algorithm [1,2] provide attackers with important side-channel information (delay, power consumption or EM radiation) that can be used to disclose the secret key of the encryption device. Differential power analysis (DPA) [3-5] is one of the most common side-channel attacks because of its simplicity and(More)
An all-digital dynamically adaptive clock distribution mitigates the impact of high-frequency supply voltage droops on microprocessor performance and energy efficiency. The design integrates a tunable-length delay prior to the global clock distribution to prolong the clock-data delay compensation in critical paths during a droop. The tunable-length delay(More)
A graphics execution core in 22nm improves energy efficiency across a wide DVFS range, from the near-threshold voltage (NTV) region, where circuit assist lowers intrinsic VMIN, to the turbo region, where adaptive clocking reduces the voltage-droop guard-band [1]. When powered with a shared rail, however, energy is wasted in the core if other blocks demand(More)