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—The performance and threshold voltage variability of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are compared against those of conventional bulk MOSFETs via 3-D device simulation with atomistic doping profiles. Compact (analytical) modeling is then used to estimate six-transistor SRAM cell performance metrics (i.e., read and write margins, and(More)
300 mm SOI wafers with sub-100nm thick active Si layers are currently produced in large quantities and used in advanced microprocessor circuits. To further enhance the performance of the next generation of devices, strained Si layers on insulator are being developed. The lattice mismatch between silicon and SiGe alloys, combined with layer transfer through(More)
Current status and future perspectives for SOI (silicon-on-insulator) using Smart Cut technology will be reviewed. First, industrial growth of SOI production mainly driven by MRJ and low-power LSI applications will be presented, with a focus on the rapid growth of 300mm SOI wafer production and advancement of Si thickness control. Next, versatility of the(More)
Current status of strained-SOI (sSOI) substrate technology is reviewed along with relevant device-level strain optimization. Smart Cut trade enables to transfer a tensile-strained Si film, grown on Si<sub>0.8</sub>Ge<sub>0.2</sub>, onto a 300mm Si wafer, with excellent thickness uniformity and preserved stress. The pile-ups (PUs) have been eliminated and(More)
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