Carlos Ivan Castro Marquez

Learn More
Formal techniques provide exhaustive design verification, but computational margins have an important negative impact on its efficiency. Sequential equivalence checking is an effective approach, but traditionally it has been only applied between circuit descriptions with one-to-one correspondence for states. Applying it between RTL descriptions and(More)
Among the current verification techniques, functional verification has received important attention, since it represents an alternative that keeps HDL validation costs low throughout the circuit's design cycle. Functional verification is based in testbenches, and it works by exploring the whole (or relevant) model's functionality, applying sets of(More)
  • 1