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Formal verification by symbolic evaluation of partially-ordered trajectories
TLDR
Symbolic trajectory evaluation provides a means to formally verify properties of a sequential system by a modified form of symbolic simulation. Expand
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Asynchronous Circuits
TLDR
This is a very reasonable book that should be read. Expand
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Generalized Symbolic Trajectory Evaluation - Abstraction in Action
TLDR
Generalized STE (Symbolic Trajectory Evaluation) is a unified model checking framework that gives one the power to choose and seamlessly adjust the level of abstraction in a model as well as in a specification during a verification effort. Expand
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An industrially effective environment for formal hardware verification
TLDR
The Forte formal verification environment for datapath-dominated hardware is described and the elements of the verification methodology that make it effective in practice are also described. Expand
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Formal verification using parametric representations of Boolean constraints
TLDR
We describe the use of parametric representations of Boolean predicates to encode data-space constraints and significantly extend the capacity of formal verification. Expand
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Introduction to generalized symbolic trajectory evaluation
TLDR
Symbolic trajectory evaluation (STE) is a lattice-based model checking technology that uses a form of symbolic simulation to express and verify properties over finite time intervals. Expand
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Formal hardware verification by symbolic ternary trajectory evaluation
TLDR
Symbolic trajectory evaluation is a new approach to formal hardware verification combining the circuit modeling capabilities of symbolic logic simulation with some of the analytic methods found in temporal logic model checkers. Expand
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Symbolic Trajectory Evaluation
TLDR
We use Voss’s fully programmable script language, FL, to implement the compositional theory presented in Section 5.3 of the paper. Expand
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The formal verification of a pipelined double-precision IEEE floating-point multiplier
TLDR
We present the formal verification of a radix-eight, pipelined, IEEE double-precision floating-point multiplier using a mixture of model-checking and theorem-proving techniques in the Voss hardware verification system. Expand
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