Carl Edward Gray

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A programmable FPGA-based digital logic circuit is enhanced with high-speed, positive emitter-coupled logic (PECL) to create a standalone tester for a self routing optical packet switching network. This tester serves as a test bed for evaluating high-speed electrical to optical conversion techniques and the difficulties associated with burst packet(More)
In this paper we present the design and performance characteristics for a custom test system developed to characterize a DWDM optically-routed packet switching network (called "Data Vortex"). The existing demonstration system supports aggregate data rates of 20 to 32 Gbps using 8 optical payload wavelengths each running at 2.5-4.0 Gbps. Several other(More)
This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. A common CMOS FPGA-based logic core(More)
DESA Th e Department of Economic and Social Aff airs of the United Nations Secretariat is a vital interface between global policies in the economic, social and environmental spheres and national action. Th e Department works in three main interlinked areas: (a) it compiles, generates and analyses a wide range of economic, social and environmental data and(More)
This paper presents the design and performance characteristics of a system designed to interface between a PCI Express port and an optical packet switched network as well as provide inline test capability for the whole system. A single lane of PCI Express traffic is inverse multiplexed across eight parallel channels and retransmitted in a burst packet at(More)
nic nic nic nic nic nic nic nic tx tx tx tx rx rx rx rx The Data Vortex topology relies on a banyan-like addressing structure while incorporating a unique deflection routing scheme as an internalized buffering mechanism, making it ideal for realization with photonic devices. The implemented 12×12 system is of size (C,H,A) = (3,4,3), and the simulations(More)
iv To my amazing, wonderful, loving wife Heather. vi ACKNOWLEDGMENTS The completion of a dissertation is a long and arduous process, and I never could have done it alone. Here I would like to thank the many, many people who have helped and supported me along the way. First, my thanks to my adviser, Professor Hsien-Hsin S. Lee for giving me the opportunity(More)
This paper describes and compares two methods for producing digital test signals up to 24 Gbps. Prototypes are experimentally characterized to determine signal quality, and the two methods are demonstrated and compared. The residual timing errors are dominated by jitter. Typical random jitter (RJ) is about 1.17ps to 1.4ps (RMS) including system measurement(More)