Carl Edward Gray

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—Multiwavelength optical messages encoded in a bit-parallel fashion are successfully routed through five switching nodes of a 12-port optical packet switching interconnection network. The data payloads are entirely recovered and processed at the destination node using an embedded clock signal with a measured clock-to-data skew tolerance window of 150 ps.
A programmable FPGA-based digital logic circuit is enhanced with high-speed, positive emitter-coupled logic (PECL) to create a standalone tester for a self routing optical packet switching network. This tester serves as a test bed for evaluating high-speed electrical to optical conversion techniques and the difficulties associated with burst packet(More)
In this paper we present the design and performance characteristics for a custom test system developed to characterize a DWDM optically-routed packet switching network (called "Data Vortex"). The existing demonstration system supports aggregate data rates of 20 to 32 Gbps using 8 optical payload wavelengths each running at 2.5-4.0 Gbps. Several other(More)
This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. A common CMOS FPGA-based logic core(More)
DESA Th e Department of Economic and Social Aff airs of the United Nations Secretariat is a vital interface between global policies in the economic, social and environmental spheres and national action. Th e Department works in three main interlinked areas: (a) it compiles, generates and analyses a wide range of economic, social and environmental data and(More)
This paper presents the design and performance characteristics of a system designed to interface between a PCI Express port and an optical packet switched network as well as provide inline test capability for the whole system. A single lane of PCI Express traffic is inverse multiplexed across eight parallel channels and retransmitted in a burst packet at(More)
nic nic nic nic nic nic nic nic tx tx tx tx rx rx rx rx The Data Vortex topology relies on a banyan-like addressing structure while incorporating a unique deflection routing scheme as an internalized buffering mechanism, making it ideal for realization with photonic devices. The implemented 12×12 system is of size (C,H,A) = (3,4,3), and the simulations(More)