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Secure Memory Accesses on Networks-on-Chip
TLDR
This paper presents a secure NoC architecture composed of a set of data protection units (DPUs) implemented within the network interfaces, and focuses on the dynamic updating of the DPUs to support their utilization in dynamic environments, and on the utilization of authentication techniques to increase the level of security. Expand
An instruction-level energy model for embedded VLIW architectures
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power consumptionExpand
Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems
TLDR
Analytical and experimental analyses are presented showing the improved performance of the encoding scheme when compared to both binary and Gray addressing schemes, the latter being widely accepted as the most efficient method for address bus encoding. Expand
ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration
TLDR
An efficient DSE methodology for application-specific MPSoC is proposed that is efficient in the sense that it is capable of finding a set of good candidate architecture configurations by minimizing the number of simulations to be executed. Expand
A security monitoring service for NoCs
TLDR
A monitoring system for NoC based architectures, whose goal is to help detect security violations carried out against the system and analyse overhead associated with the ASIC implementation of the monitoring system. Expand
An industrial design space exploration framework for supporting run-time resource management on multi-core systems
TLDR
A run-time manager operating system module is in charge of matching the specified QoS with the available platform resources by manipulating the overall degree of task-level parallelism of each application as well as the frequency of operation of each of the system cores. Expand
Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations
TLDR
This paper presents the attacks most likely to address networks-on-chips (NoCs) architectures and suggests the use of the NoC as a mean to monitor and detect unexpected system behaviors. Expand
Address bus encoding techniques for system-level power optimization
TLDR
This paper presents innovative encoding techniques suitable for minimizing the switching activity of system-level address buses, and targets the reduction of the average number of bus line transitions per clock cycle. Expand
Multi-objective design space exploration of embedded systems
TLDR
A Design Space Exploration (DSE) framework to simulate the target system and to dynamically profile the target applications and to reduce the overall exploration time by computing an approximated Pareto set of configurations with respect to the selected figures of merit. Expand
Power estimation for architectural exploration of HW/SW communication on system-level buses
TLDR
The proposed model can be effectively adopted to appropriately configure the memory hierarchy and the system bus architecture from the power standpoint and show how the variation of cache parameters and the introduction of bus encoding at the different levels on theMemory hierarchy can affect the system power dissipation. Expand
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