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AlphaSort: a RISC machine sort
A new sort algorithm, called AlphaSort, demonstrates that commodity processors and disks can handle commercial batch workloads and proposes two new benchmarks: Minutesort: how much can you sort in a minute, and DollarSort: how to sort for a dollar.
Web server performance modeling using an M/G/1/K*PS queue
- J. Cao, M. Andersson, C. Nyberg, M. Kihl
- Computer Science10th International Conference on…
- 2 April 2003
An M/G/1/K*PS queueing model of a web server that is conceptually simple, easy to estimate model parameters and fit well to the experimental outcome is presented.
Exploring bottlenecks in market-driven requirements management processes with discrete event simulation
Alphasort: A cache-sensitive parallel external sort
- C. Nyberg, Tom Barclay, Z. Cvetanovic, J. Gray, D. Lomet
- Computer ScienceThe VLDB Journal
- 1 October 1995
A new sort algorithm, called AlphaSort, demonstrates that commodity processors and disks can handle commercial batch workloads and argues that modern architectures require algorithm designers to re-examine their use of the memory hierarchy.
Investigation of overload control algorithms for SCPs in the intelligent network
The authors investigate overload control mechanisms for theSCPs and show that, to have fairness among the SSPs, the SCPs must control the acceptance rate.
Performance / Price Sort and PennySort
This paper documents this and proposes that the PennySort benchmark be revised to Performance/Price sort: a simple GB/$ sort metric based on a two-pass external sort.
Admission Control with Service Level Agreements for a Web Server
This paper investigates two overload control strategies with per formance bounds for a web server, and bound average response times and throughputs for all service classes.
A Routing Protocol for LoRA Mesh Networks
- Dan Lundell, A. Hedberg, C. Nyberg, Emma Fitzgerald
- Computer ScienceIEEE 19th International Symposium on "A World of…
- 1 June 2018
A new routing protocol is presented to enable mesh networking with LoRa, allowing for multihop networking between gateways to extend coverage and has shown its effectiveness in both laboratory tests and a field trial in a real-world LoRa deployment.
Architecture of a VLSI instruction cache for a RISC
In designing a VLSI instruction cache for a RISC microprocessor the authors have uncovered four ideas potentially applicable to other V LSI machines that provide expansible cache memory, increased cache speed, reduced program code size, and decreased manufacturing costs.
Performance Modeling of an Apache Web Server with Bursty Arrival Traffic
- M. Andersson, Jianhua Cao, M. Kihl, C. Nyberg
- Computer ScienceInternational Conference on Internet Computing
This work presents a queueing model of an Apache web server that uses bursty arrival traffic and the performance metrics predicted by the model fit well to the experimental outcome.