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Modified Montgomery modular multiplication and RSA exponentiation techniques
Modified Montgomery multiplication and associated RSA modular exponentiation algorithms and circuit architectures are presented. These modified multipliers use carry save adders (CSAs) to perform
Hardware Elliptic Curve Cryptographic Processor Over$rm GF(p)$
A novel hardware architecture for elliptic curve cryptography (ECC) over GF(p) is introduced, based on a new unified modular inversion algorithm that offers considerable improvement over previous ECC techniques that use Fermat's Little Theorem for this operation.
High-radix systolic modular multiplication on reconfigurable hardware
Novel high radix systolic array Montgomery multiplier designs are presented, as it is believed that the inherent regular structure and absence of global interconnect associated with these, make them well-suited for implementation on modern FPGAs.
FPGA Montgomery multiplier architectures - a comparison
Novel FPGA architectures for the SOS, CIOS and FIOS Montgomery multiplication algorithms are presented, and it is shown that one can tailor the multiplier architectures to be area efficient, time efficient or a mixture of both, by choosing a particular word size.
High-speed hardware architectures of the Whirlpool hash function
High-speed hardware architectures of the Whirlpool hash function are presented in this paper. A full look-up table (LUT) based design is shown to be the fastest method by which to implement the
An FPGA elliptic curve cryptographic accelerator over GF(p)
A new FPGA architecture for performing the arithmetic functions needed in elliptic curve cryptographic primitives over GF(p) is presented. The embedded 18×18-bit multipliers and fast carry look-ahead
Improved Montgomery modular inverse algorithm
A new, single and unified Montgomery modular inverse algorithm, which performs both classical and Montgomery modular inversion, is proposed. This reduces the number of Montgomery multiplication
FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p)
New FPGA architectures for the ordinary Montgomery multiplication algorithm and the FIOS modular multiplication algorithm are presented. The embedded 18 /spl times/ 18-bit multipliers and fast carry
Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication
A generic coarsely integrated operand scanning (CIOS) architecture that provides high speed Montgomery modular multiplication is presented, and to the authors' knowledge this is the fastest Montgomery multiplication architecture reported in the literature.