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Physical understanding of alloy scattering in SiGe channel for high-performance strained pFETs
For devices beyond the 14nm node, it is important to investigate performance boosters such as high mobility channels. Although pure Ge offers a higher hole mobility than Si, conventional problemsExpand
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Impact of BTBT, stress and interface charge on optimum Ge in SiGe pMOS for low power applications
  • S. Dhar, H. Noh, +12 authors W. Choi
  • Materials Science
  • International Conference on Simulation of…
  • 1 September 2016
The feasibility of medium-high fraction SiGe based FinFET pMOS devices for a sub-10nm CMOS logic technology from a performance (IEFF @ fixed IOFF) standpoint is evaluated, considering three keyExpand
  • 3
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Highly Strained Si pFinFET on SiC With Good Control of Sub-Fin Leakage and Self-Heating
Investigating of ON-current boosting, short channel effect (SCE), and self-heating effect in Si pFinFET on a SiC stress relaxed buffer (SRB) layer is presented compared with SiGe pFinFET on aExpand
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Physics-augmented Neural Compact Model for Emerging Device Technologies
This paper proposes a novel compact modeling framework based on artificial neural networks and physics informed machine learning techniques. This physics- augmented neural compact model shows highlyExpand
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Nanoscale-nMOSFET junction design: Quantum transport approach
Employing quantum transport solver, we have demonstrated the impact of junction proximity and abruptness on device performance. To entail the discrete dopant effect accurately, impurity scatteringExpand
  • 1
Artificial Neural Network-Based Compact Modeling Methodology for Advanced Transistors
The artificial neural network (ANN)-based compact modeling methodology is evaluated in the context of advanced field-effect transistor (FET) modeling for Design-Technology-Cooptimization (DTCO) andExpand
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The Impact of Dislocation on Bulk -Si FinFET Technologies: Physical Modeling of Strain Relaxation and Enhancement by Dislocation
The optimal position of dislocation stress memorization technique (DSMT) to maximize n-FinFET performance as well as the stacking fault (SF) number, [Ge] concentration limit and p-FinFET DC tradeoffExpand
  • 1
A Novel Approach for Semiconductor Etching Process with Inductive Biases
We introduce the state-of-the-art deep learning model to predict the etching profiles for semiconductor etching process. Expand
Real-Time TCAD: a new paradigm for TCAD in the artificial intelligence era
This paper presents a novel approach to enable real-time device simulation and optimization. Expand