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Parametric yield management for 3D ICs: Models and strategies for improvement
TLDR
We develop a model to quantify the impact of process variations on the parametric yield of 3D ICs, and then we propose a number of integration strategies that use a graph-theoretic framework to maximize the performance,Parametric yield and profits of 3 D ICs. Expand
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An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration
TLDR
This work has been partially supported by the ARTIST2 EU Network of Excellence on Embedded Systems. Expand
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Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems
TLDR
We investigate how transactional memory can be adapted for embedded systems. Expand
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NBTI-aware data allocation strategies for scratchpad memory based embedded systems
While performance and power continue to be important metrics for embedded systems, as CMOS technologies continue to shrink, new metrics such as variability and reliability have emerged as limitingExpand
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V 5116 SGR , AN ECLIPSING SUPERSOFT POST-OUTBURST NOVA ?
V5116 Sgr (Nova Sgr 2005 No. 2), discovered on 2005 July 4, was observed with XMM-Newton in March 2007, 20 months after the optical outburst. The X-ray spectrum shows that the nova had evolved to aExpand
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Energy efficient synchronization techniques for embedded architectures
TLDR
We evaluate the energy-efficiency and performance of a number of synchronization mechanisms adapted for embedded devices. Expand
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SoC-TM: Integrated HW/SW support for transactional memory programming on embedded MPSoCs
TLDR
In this paper we present SoC-TM, an integrated HW/SW solution for transactional programming on embedded MP-SoCs. Expand
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Sur l'élasticité du caoutchouc
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Strategies for improving the parametric yield and profits of 3D ICs
TLDR
We develop a model to quantify the impact of process variations on the parametric yield of 3D ICs, and then we propose a number of integration strategies that use a graph-theoretic framework to maximize the performance,Parametric yield and profits of 3 D ICs. Expand
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A hardware/software framework for supporting transactional memory in a MPSoC environment
TLDR
We demonstrate a complete hardware transactional memory solution for an embedded multi-core architecture, consisting of a cache-coherent ARM-based cluster, similar to ARM's MPCore, and show that it is a promising solution, even for resource-constrained embedded multiprocessors. Expand
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