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A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
TLDR
A 1.2 V 10-bit 100 MS/s Successive Approximation ADC achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Expand
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An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC
TLDR
An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. Expand
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A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure
TLDR
An 8b 1GS/s ADC is presented that interleaves two 2b/cycle SARs. Expand
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Split-SAR ADCs: Improved Linearity With Power and Speed Optimization
  • Yan Zhu, C. Chan, +4 authors F. Maloberti
  • Computer Science, Mathematics
  • IEEE Transactions on Very Large Scale Integration…
  • 1 February 2014
TLDR
This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and Vcm-based switching. Expand
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An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS
TLDR
This paper presents an 11 bit 450 MS/s three-way time-interleaved (TI) subranging pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) that achieves a high conversion rate and accuracy with good power efficiency. Expand
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A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation
TLDR
This paper presents a 6-bit 3.4 GS/s flash ADC in 65 nm CMOS that achieves a 4x interpolation factor with simple SR-latches. Expand
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Using Biased Support Vector Machine to Improve Retrieval Result in Image Retrieval with Self-organizing Map
TLDR
We propose a novel relevance feedback technique to incorporate both inter-query and intra-query information for modifying the feature vector space and estimating the users’ target. Expand
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A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation
TLDR
This paper presents a time-interleaved pipelined-SAR ADC with on-chip offset cancellation technique. Expand
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A power effective 5-bit 600 MS/s binary-search ADC with simplified switching
TLDR
This paper proposes the design of a binary search ADC that uses two different techniques, namely, distributed-residue and folding. Expand
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