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error prone. It was demonstrated repeatedly, that SMV is a very powerful and efficient specification proofreader. Model checking with SMV has sufficient capacity to analyze complete specifications of real-life directory based cache coherency protocols, within the aggressive time schedule of a computer design project. It helped us find several problems in(More)
This work is an evaluation of Linear Quasi-Anticipation in real time domains. The evaluation is performed with experiments in two types of problem domains: pathfinding and Robocup soccer simulation. The experiments gave us valuable insights and made it possible for us to identify key issues concerning linear anticipation in dynamic and real-time domains.(More)
Summary form only given. For many VLSI designs, validation has started to dominate the total design effort. In addition, historical trends are indicating that this problem will continue to grow. For example, data from Intel's lead microprocessor design efforts shows that the number of pre-silicon bugs has increased by a factor of four for every lead project(More)
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