C. Norris Ip

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Validation of industrial designs is becoming more challenging as technology advances and demand for higher performance increases. One of the most suitable debugging aids is automatic formal veri cation. Unlike simulation, which tests behaviors under a speci c execution, automatic formal veri cation tests behaviors under all possible executions of a system.(More)
We reduce the state explosion problem in automatic verification of finite-state systems by automatically collapsing subgraphs of the state graph into abstract states. The key idea of the method is to identify state generation rules that can be inverted. It can be used for verification of deadlock-freedom, error and invariant checking and(More)
An extension to the Murφ verifier is presented to verify systems with replicated identical components. Although most systems are finite-state in nature, many of them are also designed to be scalable, so that a description gives a family of systems, each member of which has a different number of replicated components. It is therefore desirable to be able to(More)
The increasing complexity of Systems on Chip (SoC) has introduced the need for abstract executable specifications (models) covering both hardware and embedded software. The new capabilities of SystemC 2.0, such as those added for transaction-based communication and test-bench Specification and monitoring, facilitate this SoC modeling. However, an obstacle(More)