C. L. Perkins

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We present an ownership-based multiprocessor cache consistency protocol, designed for implementation by a single chip VLSI cache controller. The protocol is compared with other shared bus multiprocessor protocols, and is shown to be an improvement in terms of its additional burden on the system bus. The design has been carried through to layout in a P-Well(More)
We present a new reliability model for hard real-time systems. This is an extended Markov model, derived from an analysis of the generic properties of hard real-time systems subject to a simple random-fault model. Our model permits analysis of the run-time behaviour of a system, in order to derive the probability prooles of the system's completion/failure(More)
We present a new reliability model for hard real-time systems. This model uses a generic high-level formalism based upon a Markov c hain with a lattice structure which represents the progress of a computation, allowing both functional and time correctness of the system to be modelled. This is an improvement on traditional system reliability models which t(More)
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