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The problem of multiprogram scheduling on a single processor is studied from the viewpoint of the characteristics peculiar to the program functions that need guaranteed service. It is shown that an optimum fixed priority scheduler possesses an upper bound to processor utilization which may be as low as 70 percent for large task sets. It is also shown that(More)
We present in this paper a new algorithm for floorplan design using the method of simulated annealing. The major contributions of the paper are: 1. A new representation of floorplans (normalized Polish expressions) which enables us to carry out the neighborhood search effectively. 2. A simultaneous minimization of area and total interconnection length in(More)
A set of equally long finite sequences, the elements of which are either + 1 or 1, is said to he a complementary set of sequences if the sum of autocorrelation functions of the sequences in that set is zero except for a zero-shift term. A complementary set of sequences is said to he a mate of another set if the sum of the cross-correlation functions of the(More)
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed to minimize coupled switchings which dominate the on-chip bus power consumption. The coupling-driven bus invert method use slim encoder and decoder architecture to minimize the(More)
As technology advances, interconnection wires are placed in closer proximitg and circuits operate at higher frequencies. Consequently, reduction of crosstalk-s between interconnection wires becomes an important consideration in VLSI design. In this paper, we study the gm’dded channel routing problem with the objective of satisfying crosstalk constraints for(More)
AbstructA new scheduling algorithm for dataflow graphs with nested conditional branches is presented. The algorithm employs a bottom-up approach to transform a dataflow graph with conditional branches into an “equivalent” one that has no conditional branches. A schedule is then obtained for the latter, using a conventional scheduling algorithm, from which a(More)
We study the technology mapping problem for sequential circuits for look-up table (LUT) based field programmable gate arrays (FPGAs). Existing approaches to the problem simply remove the flip-flops (FFs), then map the remaining combinational logic, and finally put the FFs back. These approaches ignore the sequential nature of a circuit and assume the(More)
We present in this article a new approach to the synthesis problem for finite state machines with the reduction of power dissipation as a design objective. A finite state machine is decomposed into a number of <italic>coupled</italic> submachines. Most of the time, only one of the submachines will be activated which, consequently, could lead to substantial(More)
In this paper we consider the problem of clustering sequential circuits subject to a bound on the area of each cluster, with the objective of minimizing the clock period. Current algorithms address combinational circuits only, and treat a sequential circuit as a special case, by removing all flip-flops (FF’s) and clustering the combinational part of the(More)