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In this paper we propose a new model for leakage mechanism in tail-mode bits of DRAM data retention characteristics. For main-mode bits, leakage current can be attributed to junction thermal-generation leakage current. For tail-mode bits, it is found for the first time that Gate-Induced Drain Leakage (GIDL) current has a dominant impact. The root cause is(More)
A new shallow trench process for isolation of bipolar devices is shown to allow butting of the emitter-base junction to the field oxide edge, thereby greatly reducing the overall device size and parasitic capacitances. Emitter-coupled logic (ECL) ring-oscillator measurements demonstrate a significant performance leverage, where a delay of 75 ps is obtained(More)
We present an efficient and accurate method to characterize the physical thickness of ultrathin gate oxides (down to 25 /spl Aring/) and the effective polysilicon doping of advanced CMOS devices. The method is based on the model for Fowler-Nordheim (F-N) tunneling current across the gate oxide with correction in gate voltage to account for the(More)
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