In this paper we propose a new model for leakage mechanism in tail-mode bits of DRAM data retention characteristics. For main-mode bits, leakage current can be attributed to junction thermal-generation leakage current. For tail-mode bits, it is found for the first time that Gate-Induced Drain Leakage (GIDL) current has a dominant impact. The root cause isâ€¦ (More)

A model for<tex>dV/dt</tex>breakdown in power MOSFET's is proposed. This model allows quantitative analysis of<tex>dV/dt</tex>limitation in power MOSFET circuits. Experimental results show good agreement with theoretical predictions.

A new shallow trench process for isolation of bipolar devices is shown to allow butting of the emitter-base junction to the field oxide edge, thereby greatly reducing the overall device size and parasitic capacitances. Emitter-coupled logic (ECL) ring-oscillator measurements demonstrate a significant performance leverage, where a delay of 75 ps is obtainedâ€¦ (More)

We present an efficient and accurate method to characterize the physical thickness of ultrathin gate oxides (down to 25 /spl Aring/) and the effective polysilicon doping of advanced CMOS devices. The method is based on the model for Fowler-Nordheim (F-N) tunneling current across the gate oxide with correction in gate voltage to account for theâ€¦ (More)