C. H. (Kees) De Groot

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A new architecture for a vertical MOS transistor is proposed that incorporates a so-called dielectric pocket (DP) for suppression of short-channel effects and bulk punch-through. We outline the advantages that the DP brings and propose a basic fabrication process to realize the device. The design issues of a 50-nm channel device are addressed by numerical(More)
Schottky barrier (SB) Ge channel MOSFETs suffer from high drain-body leakage at the required elevated substrate doping concentrations to suppress source-drain leakage. Here, we show that electrodeposited Ni-Ge and NiGe/Ge Schottky diodes on highly doped Ge show low off current, which might make them suitable for SB p-MOSFETs. The Schottky diodes showed(More)
A simple process for the fabrication of shallow drain junctions on pillar sidewalls in sub-100-nm vertical MOSFETs is described. The key feature of this process is the creation of a polysilicon spacer around the perimeter of the pillar to connect the channel to a polysilicon drain contact. The depth of the junction on the pillar sidewall is primarily(More)
We successfully demonstrate surface-enhanced infrared spectroscopy using arrays of indium tin oxide (ITO) plasmonic nanoantennas. The ITO antennas show a strongly reduced plasmon wavelength, which holds promise for ultracompact antenna arrays and extremely subwavelength metamaterials. The strong plasmon confinement and reduced antenna cross section allows(More)
We demonstrate milling of partial antenna gaps and narrow conducting bridges with nanometer precision using a helium ion beam microscope. Single particle spectroscopy shows large shifts in the plasmonic mode spectrum of the milled antennas, associated with the transition from capacitive to conductive gap loading. A conducting bridge of nanometer height is(More)
We demonstrate that polarization conversion in coupled dimer antennas, used in phase discontinuity metasurfaces, can be tuned by careful design. By controlling the gap width, a strong variation of the coupling strength and polarization conversion is found between capacitively and conductively coupled antennas. A theoretical two-oscillator model is proposed,(More)
Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of(More)
Plasmonic devices have a unique ability to concentrate and convert optical energy into a small volume. There is a tremendous interest in achieving active control of plasmon resonances, which would enable switchable hotspots for applications such as surface-enhanced spectroscopy and single molecule emission. The small footprint and strong-field confinement(More)
We have fabricated and measured single domain wall magnetoresistance devices with sub-20 nm gap widths using a novel combination of electron beam lithography and helium ion beam milling. The measurement wires and external profile of the spin valve are fabricated by electron beam lithography and lift-off. The critical bridge structure is created using helium(More)
This paper reports electrical results on CMOS-compatible vertical transistors and logic gates with reduced overlap capacitance. It is shown that surround-gate MOSFETs, produced using the fillet local oxidation process (FILOX), have lower gate/drain overlap capacitance and consume less silicon area than comparable lateral MOSFETs. Novel logic gate(More)