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A number of code transformations for embedded multimedia applications is presented in this paper and their impact on both system power and performance is evaluated. In terms of power the transformations move the accesses from the large background memories to small buffers that can be kept foreground. This leads to reduction of the memory related power(More)
Our aim is the development of a novel probabilistic method to estimate the power consumption of a combinational circuit under real gate delay model handling temporal, structural and input pattern dependencies. The chosen gate delay model allows handling both the functional and spurious transitions. It is proved that the switching activity evaluation problem(More)
A systematic methodology for data transfer and storage optimization of multimedia algorithms realized on programmable platforms has been developed. The methodology reduces both the sizes of and the number of accesses to the array type data structures of the target algorithm. This leads to power consumption and performance improvement. In this paper the(More)
E.U. has set a special goal for 2010 which is the adoption, by at least 25%, of IPv6. IPv6 incorporates the usage of IPSec which provides cryptographic services to every data packet which is transmitted via Internet. This means that there is a major need for High Speed designs of IPSec protocol. It has been shown that the limiting factor of IPSec(More)
In this report the design and the innovative low-power design steps followed for the development of a DCS1800-GSM/DECT modem are presented. This includes a low complexity telecommunication algorithms, a low power synthesis technique for the realisation of FIR filters, an application-specific behavioural level power management and a dynamic frequency(More)
In this paper, we propose a hardware/software partitioning method for improving applications' performance in embedded systems. Critical software parts are accelerated on hardware of a single-chip generic system comprised by an embedded processor and coarse-grain reconfigurable hardware. The reconfigurable hardware is realized by a 2-Dimensional array of(More)
—The execution time improvements achieved in a generic microprocessor system by employing a high-performance data-path are presented. The data-path acts as a coprocessor that accelerates computational intensive kernel regions thereby increasing the overall performance. The data-path has been previously introduced and it is composed by Flexible Computational(More)
This paper presents a hardware/software partitioning flow for improving performance in systems-on-chip comprised by processor and Field Programmable Gate Array. Speedups are achieved by executing critical software parts on the reconfigurable FPGA logic. A generic hybrid system architecture is considered by the methodology. The partitioning flow uses an(More)
This paper presents the performance improvements by coupling a high-performance coarse-grained reconfigurable data-path with a microprocessor in a generic platform. It is composed by computational units able to realize complex operations which aid in improving the performance of time critical application parts, called kernels. A design flow is proposed for(More)
In this paper, we propose a methodology for partitioning DSP applications between the fine and coarse-grain reconfigurable hardware for improving performance. The fine-grain logic is implemented by an embedded FPGA unit, while for the coarse-grain reconfigurable hardware, a 2-Dimensional array of Processing Elements is considered. These different(More)