C. Chrisjin Gnana Suji

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Problem Statement: In this study, we had proposed a low power architecture for high speed multiplication. Approach: The modifications to the conventional shift and add multiplier includes introduction of modified error tolerant technique for addition and enabling of adder cell by current multiplication bit of the multiplier constant. The proposed(More)
The growing market of mobile, battery-powered electronic systems (e.g., cellular phones, personal digital assistants, etc.) demands the design of microelectronic circuits with low power dissipation. As density and complexity of the chips continue to increase, the difficulty in providing power dissipation might limit the functionality of the computing(More)
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