C. Andre T. Salama

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This paper describes the implementation of an asynchronous 64-state, 1/2-rate Viterbi decoder using an original architecture and design methodology. The decoder is intended for wireless communications applications, where bit rates over 100 Mb/s and minimum power consumption are sought. The choice of an asynchronous design was predicated by the power and(More)
This paper presents the design and implementation of a new 8-GHz high linearity current commutating CMOS RF mixer. The high linearity of the mixer is attributed to the novel RF transconductor stage, employing a new version of the bias-offset technique. The outstanding features of the mixer are high linearity, low voltage, low power consumption and design(More)