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In this paper an architecture is described that implements motion estimation in image coding, using a block-matching algorithm and an exhaustive search method. The architecture consists of 256 processor elements, deals with a search area of -8/+7 pels and performs 11 GOPS (subtraction, absolute value determination, accumulation and comparison). It is(More)
— In this paper, the implementation of a digital signal processor (DSP) based H.264 decoder for a multi-format set-top box is described. Baseline and Main profiles are supported. Using several software optimization techniques, the decoder has been fitted into a low-cost DSP. The decoder alone has been tested in simulation, achieving real-time performance(More)