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In this paper, the implementation of a digital signal processor (DSP) based H.264 decoder for a multiformat set-top box is described. Baseline and Main profiles are supported. Using several software optimization techniques, the decoder has been fitted into a low-cost DSP. The decoder alone has been tested in simulation, achieving real-time performance with(More)
In this paper an architecture is described that implements motion estimation in image coding, using a block-matching algorithm and an exhaustive search method. The architecture consists of 256 processor elements, deals with a search area of -8/+7 pels and performs 11 GOPS (subtraction, absolute value determination, accumulation and comparison). It is(More)
In this paper, the implementation of a Main Profile H.264 decoder based on a DM642 digital signal processor is described. An initial standard compliant raw-C decoder has been optimized in speed for the target processor. The parallelism between algorithm execution and data movement has been fully exploited using DMA. Also, critical parts of the algorithm(More)
In this paper, the implementation of a baseline profile H.264 decoder based on a DM 642 digital signal processor is described. An initial standard compliant raw-C decoder has been optimized in speed for the target processor. The parallelism between algorithm execution and data movement has been fully exploited using DMA. Also, critical parts of the(More)