Câncio Monteiro

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Numerous articles and patents on the masking of logic gates in CMOS logic styles have been reported, however, less information is available with regards to comparing the single-rail and dual-rail on masking input logic values. This paper investigates single-rail and dual-rail logic families that have been developed by the logic designers for secure logic(More)
Keywords: SCA DPA Adiabatic logic Bit-parallel cellular array multiplier AES Smart card a b s t r a c t Side-channel attacks by cryptanalysis are becoming a serious threat for cryptographers, who are designing systems that are more robust in terms of hardware and algorithm threats, aiming to thwart violations of the secrecy of securely processed(More)
This paper implements our proposed charge-sharing symmetric adiabatic logic (CSSAL) into the cellular multiplier used in finite field over GF(2<sup>m</sup>) arithmetic using secure system for resistant against side-channel attacks. To validate our proposed logic, we have evaluated the current traces and energy dissipation of the individual secure adiabatic(More)
In this paper, we present the post layout simulation result of our previously proposed charge-sharing symmetric adiabatic logic (CSSAL) in comparison with the symmetric adiabatic logic, 2N-2N2P, and the TDPL in the bit-parallel cellular multiplier over GF(2<sup>4</sup>). The transitional supply current and the power fluctuation of each logic style are(More)
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