Byoungdeog Choi

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Defect depth profiles of Cu (In1-x,Gax)(Se1-ySy)2 (CIGSS) were measured as functions of pulse width and voltage via deep-level transient spectroscopy (DLTS). Four defects were observed, i.e., electron traps of ~0.2 eV at 140 K (E1 trap) and 0.47 eV at 300 K (E2 trap) and hole traps of ~0.1 eV at 100 K (H1 trap) and ~0.4 eV at 250 K (H2 trap). The open(More)
Low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have a high carrier mobility that enables the design of small devices that offer large currents and fast switching speeds. However, the electrical characteristics of the conventional self-aligned polycrystalline silicon (poly-Si) TFTs are known to present several undesired effects,(More)
  • Seung-Ha Han, Hwan-Bae Yu, Hyun-Chul Shin, Jun-Ui Song, Hae-Bum Lee, Jung-Hyuk Choi +5 others
  • 2010
The cell integration density of the NOR flash memory is increasing rapidly. And MLC (multi-level cell) was introduced as a strong method for the evolution of high density and high performance of flash memories in mobile applications [1]. However, MLC technology requires a tight distribution of threshold voltage (Vt) compared to those of single level cell(More)
  • Jun-Woo Lee, Hwan-Woo Kim, Hyung-Joon Kim, Seog-Gyu Kim, Kyu-Pil Lee, Soo-Cheol Lee +24 others
  • 2010
As the device continues scale down to sub 0.1um, the HDP-CVD process has been widely used for the deposition of dielectric films because of its better gap-fill capability than conventional process in relatively low temperature. However, the HDP-CVD process has some potential problems including plasma-induced damage. And we know the photoconduction mechanism(More)
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