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Characterization of the Variable Retention Time in Dynamic Random Access Memory
To study the relationship between the original leakage current fluctuation and the detected variable retention time (VRT) from the retention test of dynamic random access memory (DRAM), we simulatedExpand
Characterization of an Oxide Trap Leading to Random Telegraph Noise in Gate-Induced Drain Leakage Current of DRAM Cell Transistors
An accurate method for extracting the depth and the energy level of an oxide trap from random telegraph noise (RTN) in the gate-induced drain leakage (GIDL) current of a metal-oxide-semiconductorExpand
Checkpointing Exascale Memory Systems with Existing Memory Technologies
TLDR
It is shown that exascale systems with hundreds of petabytes of memory can be constructed with commodity DRAM and SSD flash memory and that newer non-volatile memory are unnecessary, at least for the next generation. Expand
$f_{\max}$ Improvement by Controlling Extrinsic Parasitics in Circuit-Level MOS Transistor
In this letter, <i>f</i> <sub>max</sub> improvement of a circuit-level radio-frequency (RF) transistor with systematic layout variations is presented in deep-submicrometer CMOS technology. WeExpand
Study of Trap Models Related to the Variable Retention Time Phenomenon in DRAM
To study trap models related to the variable retention time (VRT) phenomenon in dynamic random access memory (DRAM), we derived equations to calculate the data retention time tret of DRAM and theExpand
Enhancing DRAM Self-Refresh for Idle Power Reduction
TLDR
The key idea behind the observation is to optimize the leakage current of DRAM cells by selectively applying different voltage levels to the DRAM cell transistors when they are active (accessed for refreshing) and idle (pre-charged) by adjusting both the word-line and body voltages. Expand
Investigation of Gate Etch Damage at Metal/High-$k$ Gate Dielectric Stack Through Random Telegraph Noise in Gate Edge Direct Tunneling Current
Plasma damage on a high-k/SiO2 dielectric at a gate edge during a dry etch process is investigated. The damage was observed to generate slow oxide traps, causing a random telegraph noise (RTN) in aExpand
Characterization of Border Trap Density With the Multifrequency Charge Pumping Technique in Dual-Layer Gate Oxide
The multifrequency charge pumping (MFCP) experiments have been investigated by many research groups for the characterization of oxide traps in high-permittivity (high-κ ) dielectricExpand
Random Telegraph Signal-Like Fluctuation Created by Fowler-Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor
We generated traps inside gate oxide in gate–drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler–Nordheim (FN) stress, and observed gateExpand
Study on Time Constants of Random Telegraph Noise in Gate Leakage Current Through Hot-Carrier Stress Test
Capture and emission time constants obtained from random telegraph noise in gate leakage current ( Ig RTN) are studied by characterizing an intentionally created trap in thin gate oxide (2.6 nm) inExpand
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