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This paper presents a high speed, non-pipelined FPGA implementation of the Rijndael algorithm (Daemen, 1999), which has been selected as the new AES algorithm by the National Institute of Standards and Technology (NIST). In this study, we have implemented both the encryption and the decryption algorithms of Rijndael on the same FPGA. All the key and data(More)
This paper presents a third-order switched-capacitor sigma-delta modulator implemented in a standard 0.35-μm CMOS process. It operates from 300 K down to 4.2 K, achieving 70.8 dB signal-to-noise-plus-distortion ratio (SNDR) in a signal bandwidth of 5 kHz with a sampling frequency of 500 kHz at 300 K. The modulator utilizes an operational transconductance(More)
This paper presents a cryogenic successive approximation register (SAR) based analog to digital converter (ADC) implemented in a standard 0.35 microm complementary metal oxide semiconductor (CMOS) process. It operates from room temperature down to 4.4 K, achieving 10.47 effective number of bits (ENOB) at room temperature. At 4.4 K, the ADC achieves 8.53(More)
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