In this paper, we present a new algorithm for standard cell global routing. The algorithm considers all of the interconnection nets simultaneously; this produces superior results since information about all of the nets is available throughout the global routing process. We formulate the global routing problem as one of finding the optimal spanning forest on… (More)
When an over-the-cell routing layer is available for standard cell layout, efficient utilization of routing space over the cells can significantly reduce layout area. In this paper, we present three physical models to utilize the area over the cells for routing in standard cell designs. We also present efficient algorithms to choose and to route a planar… (More)
In this paper, we present an accurate model for prediction of inter-connection lengths for standard cell layouts. On the designs in our test suite the estimates are within 10% of the actual layouts. Our model abstracts the important features of placement, global rout ing and channel routing. The predicted results are obtained from analysis of the net list.… (More)
New placement algorithms have been developed which are suitable for the layout of Very Large Scale Integrated (VLSI) circuits Hierarchical decomposition is used to reduce the circuit function to a size that can be comprehended by the designer and is computationally feasible to layout. At each hierarchical level the problem consists of the placement of… (More)
A new automatic IC mask layout code is described which avoids most of the problems inherent in the present generation of layout codes such as lack of flexibility, inefficient use of area, and restricted design complexity. The structured hierarchical layout approach, construction graphs, and placement and routing algorithms are outlined.
This review provides an overview of the placement function within automatic layout systems. The automatic placement problem is defined and the data abstractions are described. The discussion divides placement algorithms into two classes: constructive and iterative. Applications of the algorithms within layout systems are described. A large number of… (More)
An efficient method of producing logical combinations of integrated circuit (IC) masks in numerical form leads to a generalized design rule checking program. The union (OR), intersection (AND) and the complements, as well as topological classification and simple geometric operations, are provided through a set of LOGical MASk Checking (LOGMASC) commands,… (More)
A Circuit MAsk Translator (CMAT) code has been developed which converts integrated circuit mask information into a circuit schematic. Logical operations, pattern recognition, and special functions are used to identify and interconnect diodes, transistors, capacitors, and resistances. The circuit topology provided by the translator is compatible with the… (More)