Bryan Preas

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When an over-the-cell routing layer is available for standard cell layout, efficient utilization of routing space over the cells can significantly reduce layout area. In this paper, we present three physical models to utilize the area over the cells for routing in standard cell designs. We also present efficient algorithms to choose and to route a planar(More)
In this paper, we present an accurate model for prediction of inter-connection lengths for standard cell layouts. On the designs in our test suite the estimates are within 10% of the actual layouts. Our model abstracts the important features of placement, global rout ing and channel routing. The predicted results are obtained from analysis of the net list.(More)
2 The staggered non-uniform segmentation model (shown for tracks of type k) : : : 22 3 One-segment routing Abstract FPGAs combine the logic integration benefits of custom VLSI with the design, production, and time-to-market advantages of standard logic ICs. The Actel family of FPGAs exemplifies the row-based FPGA model. Rows of logic cells interspersed with(More)
This review provides an overview of the placement function within automatic layout systems. The automatic placement problem is defined and the data abstractions are described. The discussion divides placement algorithms into two classes: constructive and iterative. Applications of the algorithms within layout systems are described. A large number of(More)
In this paper, we present an accurate model for prediction of physical desi n characteristics, such as inter-connection lengths a n f layout areas, for standard cell layouts. This model produces accurate shape constraint functions (height versus width of the layout over a range of aspect ratios) by considering the lo ic design specification , the physical(More)