Bryan Preas

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When an over-the-cell routing layer is available for standard cell layout, efficient utilization of routing space over the cells can significantly reduce layout area. In this paper, we present three physical models to utilize the area over the cells for routing in standard cell designs. We also present efficient algorithms to choose and to route a planar(More)
In this paper, we present an accurate model for prediction of inter-connection lengths for standard cell layouts. On the designs in our test suite the estimates are within 10% of the actual layouts. Our model abstracts the important features of placement, global rout ing and channel routing. The predicted results are obtained from analysis of the net list.(More)
New placement algorithms have been developed which are suitable for the layout of Very Large Scale Integrated (VLSI) circuits Hierarchical decomposition is used to reduce the circuit function to a size that can be comprehended by the designer and is computationally feasible to layout. At each hierarchical level the problem consists of the placement of(More)
2 The staggered non-uniform segmentation model (shown for tracks of type k) : : : 22 3 One-segment routing Abstract FPGAs combine the logic integration benefits of custom VLSI with the design, production, and time-to-market advantages of standard logic ICs. The Actel family of FPGAs exemplifies the row-based FPGA model. Rows of logic cells interspersed with(More)
A new automatic IC mask layout code is described which avoids most of the problems inherent in the present generation of layout codes such as lack of flexibility, inefficient use of area, and restricted design complexity. The structured hierarchical layout approach, construction graphs, and placement and routing algorithms are outlined.
In this paper, we present an accurate model for prediction of physical desi n characteristics, such as inter-connection lengths a n f layout areas, for standard cell layouts. This model produces accurate shape constraint functions (height versus width of the layout over a range of aspect ratios) by considering the lo ic design specification , the physical(More)
A Circuit MAsk Translator (CMAT) code has been developed which converts integrated circuit mask information into a circuit schematic. Logical operations, pattern recognition, and special functions are used to identify and interconnect diodes, transistors, capacitors, and resistances. The circuit topology provided by the translator is compatible with the(More)