Bruno de Abreu Silva

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Tool Flow Proposal In this research, we present a work in progress tool to exploit power/performance optimization techniques in FPGA-based asymmetric multi-core systems. The tool flow, which is proposed in Figure 1, is divided in two phases: compilation and execution time. In the first phase, the application code is given as input to the ROSE-based(More)
Combining dataflow concepts with reconfigurable computing provides a great potential to exploit the application parallelism efficiently. However, to express such parallelism cannot be a trivial task. Therefore, there is a great effort to automatically translate programs originally written in procedural languages (like C and Java) into dataflow architectures(More)
In this paper, the acceleration of algorithms using a design of a field pro-grammable gate array (FPGA) as a prototype of a static dataflow architecture is discussed. The static dataflow architecture using operators interconnected by parallel buses was implemented. Accelerating algorithms using a dataflow graph in a reconfigurable system shows the potential(More)
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