Learn More
Heterogeneous Multi-core Processor (HMP) is a set of cores exposing the same instruction set architecture (ISA). The cores in HMPs can differ relative to performance, area, power, and micro-architecture design. Many researchers have investigated HMPs as an alternative to optimize the relationship between power consumption and performance. Usually, the(More)
In embedded systems, energy efficiency is the new fundamental performance limiter. Considering that, many techniques were applied at different development levels, such as co-design, compilers, schedulers, run-time management, and applications. The fusion of techniques from different levels has also been exploited to increase the optimization opportunities.(More)
Combining dataflow concepts with reconfigurable computing provides a great potential to exploit the application parallelism efficiently. However, to express such parallelism cannot be a trivial task. Therefore, there is a great effort to automatically translate programs originally written in procedural languages (like C and Java) into dataflow architectures(More)
In this paper, the acceleration of algorithms using a design of a field pro-grammable gate array (FPGA) as a prototype of a static dataflow architecture is discussed. The static dataflow architecture using operators interconnected by parallel buses was implemented. Accelerating algorithms using a dataflow graph in a reconfigurable system shows the potential(More)
With the number of cores increase in systems-on-chip (SoC), bus-based approach began facing challenges to support internal communication. An alternative that has been explored is the network-on-chip (NoC), an approach that proposes to use common network knowledge on SoC projects internal communication. The standards non-adoption in the NoC components(More)
  • 1